1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a floating body cell (hereinafter referred to as “FBC”) type capacitorless RAM (Random Access Memory) which is electrically isolated from a substrate by use of an insulating material.
2. Description of the Related Art
In conventional DRAMs, electric charges are accumulated in capacitors to store information. In order to achieve a high degree of integration, the footprint of individual capacitors has been increasingly miniaturized, so a configuration of a high aspect ratio is used to provide a required capacitance, making the fabrication thereof more difficult. In order to address this problem, a cell (FBC) has been proposed which stores information using the floating body effect of transistor without using a capacitor. For example, FBC type RAM has been described in U.S. Pat. No. 6,969,662, National Publication of International Patent Application No. 2004-535669, Japanese Patent Laid-Open No. 2000-340679, EP1180799 and the like.
In FBC type RAM, many carriers are accumulated in floating body of a field effect transistor (FET) formed on SOI (Silicon On Insulator) substrate to store data. For example, in an operation of writing and reading data in n-type FET cell, it is defined for the convenience of explanation that a state where a larger number of holes are accumulated in floating body of p-type semiconductor is “1”, and a state where a smaller number of holes are accumulated in floating body of p-type semiconductor is “0”; in this case, when the cell transistor is biased to a saturated state and holes generated by impact ionization are accumulated in p-type body, “1” is written. Meanwhile, when the p-n junction between p-type body and n-type source-drain is forward biased to clear out holes accumulated in p-type body, “0” is written. Further, in a reading operation, based on the floating body effect that the threshold voltage of transistor varies according to the number of holes accumulated in p-type body, stored data is differentiated by utilizing the fact that the current of cell of “1” is larger than that of “0”.
However, according to the related art, the floating body effect cannot be satisfactorily kept for a desired period of time. More specifically, when DRAM using capacitor is replaced with FBC type RAM, there causes a problem that the time period of accumulating and holding carriers in body is too short, i.e., the refresh cycle time is too short. For example, referring to Oyo Buturi, vol. 75, No. 9, pp. 1131-1135 (2006), FIG. 6(B), worst-bit failure occurs at an interval of 10 msec, but it is needed to lengthen the interval to several hundred msec or more from a viewpoint of suppressing the power consumption.
Thus, it is desirable to provide a capacitorless RAM in which the retention time is increased so that the refresh cycle time is lengthened and the power consumption is significantly reduced.